Problem executing multiple commands Rc663 with Desfire EV1 card

[Aart Scheepers]

Hi,

I am trying to send multiple commands to the Mifare Desfire card, using one of the JCF examples for the RC663.
The code listed below, (after the initialization, not included) runs once correct. The Read FIFO command lists all application id's, with 2 bytes upfront, value 0x02, 0x00.
But when re-entering the loop, after the TRansceive command, nothing is in the FIFO.

What am I missing?
Does someone have a JCF-file with multiple desfire commands?

	while (1) {

			Rc663WriteRegister(PHHAL_HW_RC663_REG_TXDATANUM, 0x08); //    SR  2E 08



//> Enable CRC.

//   SR  2C 19

//   SR  2D 19

//   SR  0C 00



			Rc663WriteRegister(PHHAL_HW_RC663_REG_TCONTROL,

					PHHAL_HW_RC663_BIT_T1STARTSTOPNOW

							| PHHAL_HW_RC663_BIT_T0STARTSTOPNOW);

// Clear IRQ

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0EN, 0x00); //    SR  08 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1EN, 0x00); //    SR  09 00



// Set T0,T1 reload values

			Rc663WriteRegister(PHHAL_HW_RC663_REG_T0RELOADHI, 0x3E); //    SR 10 3E

			Rc663WriteRegister(PHHAL_HW_RC663_REG_T0RELOADLO, 0x58); //    SR 11 58

			Rc663WriteRegister(PHHAL_HW_RC663_REG_T1RELOADHI, 0x00); //    SR 15 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_T1RELOADLO, 0x00); //    SR 16 00



// Terminate any running command, Flush FiFo

			Rc663WriteRegister(PHHAL_HW_RC663_REG_COMMAND, 0x00); //     SR 00 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_FIFOCONTROL, 0xB0); //     SR 02 B0



// Clear all IRQ 0,1 flags

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0, 0x7F); //     SR 06 7F

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1, 0x7F); //     SR 07 7F

//***************************************

//> Write command data into FIFO

			Rc663WriteRegister(PHHAL_HW_RC663_REG_FIFODATA, 0x02); //     SR 05 02        // PCB: no Cid, no Nad, I(0)0 - Frame

			Rc663WriteRegister(PHHAL_HW_RC663_REG_FIFODATA, 0x6a); //     SR 05 60        // Data  --  Desfire Get application Ids command



//> Start the command (Transcieve)

			Rc663WriteRegister(PHHAL_HW_RC663_REG_COMMAND, 0x07); //     SR 00 07



// Wait until the command is finished

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0EN, 0x18); //     SR 08 18          // Enable IRQ0 interrupt sources

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1EN, 0x42); //     SR 09 42          // Enable IRQ1 interrupt sources

			do {

//	????? ::: L_ExChange1Tx

				ior = Rc663ReadRegister(PHHAL_HW_RC663_REG_IRQ1); //    GR 07                         // read into IOR

//	????? JNM IOR 40 40 L_ExChange1Tx

			} while ((ior & 0x40) != 0x40);



// Clear IRQ 0,1 interrupt sources

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0EN, 0x00); //    SR 08 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1EN, 0x00); //    SR 09 00



//> Wait until reception. Enable IRQ0 interrupt sources

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0, 0x40); //    SR 06 40



			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0EN, 0x54); //    SR 08 54

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1EN, 0x42); //    SR 09 42

			do {

//	????? ::: L_ExChange1Rx

				ior = Rc663ReadRegister(PHHAL_HW_RC663_REG_IRQ1); //    GR 07

//	????? JNM IOR 40 40 L_ExChange1Rx

			} while ((ior & 0x40) != 0x40);



// Read IRQ 0,1 Status register

			ior = Rc663ReadRegister(PHHAL_HW_RC663_REG_IRQ0); //    GR  06

			ior = Rc663ReadRegister(PHHAL_HW_RC663_REG_IRQ1); //    GR  07



//> Read FIFO

			uint8_t buf[100];for (i=0; i<100;i++) { buf = 0xff;}

			ior = Rc663ReadRegister(PHHAL_HW_RC663_REG_FIFOLENGTH); //    GR  04                     // FIFO length

//   JNE IOR 0A END             // Response length of DesFire "Get application IDs" command

			for (i = 0; i < ior; i++) {

//	????? MOV ML7 IOR

//	????? ::: L_ExChange1

				buf = Rc663ReadRegister(

						PHHAL_HW_RC663_REG_FIFODATA); //    GR  05

//	????? DEC ML7

//	????? JNE ML7 00 L_ExChange1

			}

// Clear IRQ 0,1 interrupt sources

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ0EN, 0x00); //    SR 08 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_IRQ1EN, 0x00); //    SR 09 00



// Stop any command. Flush FiFO

			Rc663WriteRegister(PHHAL_HW_RC663_REG_COMMAND, 0x00); //    SR 00 00

			Rc663WriteRegister(PHHAL_HW_RC663_REG_FIFOCONTROL, 0xB0); //    SR 02 B0

		}

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[TapLinx Support]

Hi Aart,

It seems your question is not a MIFARE SDK/TapLinx topic. At general, reader related questions are better located at the forum here:

http://www.nxp.com/support/sales-and-support:SUPPORTHOME

Regards,
The TapLinx Team

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